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7.5 References

1. Joseph A. Fisher, Global code generation for instruction-level parallelism: Trace Scheduling-2. Tech. Rep. HPL-93-43, Hewlett-Packard Laboratories, June 1993.

2. Joseph A. Fischer, Very Long Instruction Word Architectures and the ELI-512, Proceedings of the 10'th Symposium on Computer Architectures, pp. 140-150, IEEE, June, 1983.

3. Joseph A. Fisher, Very Long Instruction Word Architectures and the ELI-512. 25 Years ISCA: Retrospectives and Reprints 1998: 263-273

4. M. Schlansker, B. R. Rau, S. Mahlke, V. Kathail, R. Johnson, S. Anik, and S. G. Abraham, Achieving high levels of instruction-level parallelism with reduced hardware complexity. Technical report, Technical Report HPL-96-120, Hewlett Packard Laboratories, Feb. 1997.

5. M. Schlansker, B. R. Rau. Epic: An Architecture for Instruction Level Parallel Processors. Technical report, Technical Report HPL-1999-111, Hewlett Packard Laboratories, Feb. 2000.

6. Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek, Lopez-Lagunas, Abelardo, Peter R. Mattson, and John D. Owens. A bandwidth-efficient architecture for media processing. In Proc. 31st Annual International Symposium on Microarchitecture, Dallas, TX, November 1998.

7. Intel Corporation. Itanium Processor Microarchitecture Reference for Software Optimization. Intel Corporation, March 2000

8. Intel Corporation. Intel IA-64 Architecture Software Developer's Manula, Volume 3: Instruction Set Reference. Intel Corporation, January 2000

9. Intel Corporation. IA-64 Application Developer's Architecture Guide. Intel Corporation, May 1999

10. P.G. Lowney, S.M. Freudenberger, T.J. Karzes, W.D. Lichtenstein, R.P. Nix, J.S. O'Donnell, and J.C. Ruttenberg. The Multiflow trace scheduling compiler. Journal of Supercomputing, 7, 1993.

11. R. E. Hank, S. A. Mahlke, J. C. Gyllenhaal, R. Bringmann, and W. W. Hwu, Superblock formation using static program analysis, in Proc. 26th Ann. Int'l. Symp. on Microarchitecture, (Austin, TX), pp. 247-255, Dec. 1993.

12. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann, Effective compiler support for predicated execution using the hyperblock, in Proceedings of the 25th International Symposium on Microarchitecture, pp. 45-54, December 1992.

13. James C. Dehnert, Peter Y. T. Hsu, Joseph P. Bratt, Overlapped Loop Support in the Cydra 5 in Proc. ASPLOS 89, pp. 26-38.

14. Alexander Klaiber, The Technology Behind Crusoe Processors. Transmeta Corp, 2000.

next up previous contents
Next: About this document ... Up: 7 Scheduling Algorithms for Previous: 7.4 The Future of   Contents
Binu K. Mathew