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4.6 Score board

To accommodate branch prediction and the variable latency of memory accesses because of cache hits and misses, some amount of score boarding is required. Though we will not describe the details of the scoreboard here, it should be emphasized that the scoreboard and control logic for a VLIW processor like the Defoe is much simpler than that of a modern super scalar processor because of the lack of out of order execution and speculation.

Binu K. Mathew