The design goal of the perception processor was to achieve high performance for perceptual algorithms at low power. For stream computations, a very important consideration is whether a system has sufficient throughput to be able to process the data rate in real time. Since dynamic energy consumption is directly proportional to operating frequency, one method for achieving this goal is to exploit high levels of instruction level parallelism for stylized applications without a paying a high price in terms of hardware complexity. The details of this approach were discussed in Chapter 3. Before the details are presented it is important to note a few details.
- With the exception of Figures 10.1 and 10.7, the Y axis of all graphs use a logarithmic scale on account of the large range of data.
- Energy, energy delay product, energy delay squared product and power numbers in all the graphs in this chapter are normalized to a process. Since the perception processor and the Pentium are both implemented in processors, their normalized results correspond to the actual results. Only the XScale and ASIC numbers are actually scaled.
- In this chapter the terms average and mean refer to the geometric mean.
- 10.4.1 Instruction Level Parallelism
- 10.4.2 Power Consumption
- 10.4.3 Throughput
- 10.4.4 Energy Consumption
- 10.4.5 Energy Delay Product
- 10.4.6 Energy Delay Squared Product
- 10.4.7 Clock Gating
- 10.4.8 The Cost of Generality