3. Principles Behind Dynamic Power Reduction

Power consumption in CMOS circuits consists primarily of static power dissipated by leakage currents and dynamic power, which is in turn comprised of short circuit dissipation and the switching power consumed while charging and discharging load capacitances. Though subthreshold leakage current was a small component of power consumption in past processes with $0.25\mu$ and larger feature sizes, it is fast becoming a large component in processes with smaller feature sizes. Architectures that expose power management to the operating system and application software can play an important role in reducing leakage power. A combination of software and hardware mechanisms can intelligently power down parts of a system that are not in active use. The most effective solutions to the leakage current problem are at the circuit and process level. Circuit design styles that use gated Vdd and stacked transistors have been shown to greatly reduce the magnitude of the problem, but they also decrease performance [78,53]. CMOS processes with multiple threshold voltages (MTCMOS) provide another solution to the leakage power problem. They also contribute to design flexibility since fast leaky transistors can be used in critical paths to enhance performance and slow energy efficient transistors can be used in noncritical parts of the circuit. How to take advantage of this flexibility in large circuits synthesized from a hardware description language (HDL) is an area of active research [93].

While a CMOS gate is switching state, there is a short period of time during which the N and P transistors are simultaneously on, which leads to short-circuit current flowing between the power and ground terminals. The magnitude of this current increases with reductions in $V_{t}$. It also increases when the rise and fall times of the input waveform are slow [109]. As in the case of leakage current there is very little that can be done at the architecture level to solve the problem. The process level solution of using high $V_{t}$ devices and circuit design styles that ensure rapid rise and fall times alleviate the severity of the problem.

The architectural options developed in this research are evaluated using transistor level circuit simulations. These Spice simulations consider both the short circuit and the leakage components of power consumption. However, since there is not much that can be done at the architecture level, this research is focused entirely on CMOS dynamic power dissipated by repeated charging and discharging of load capacitances - a problem for which architecture level solutions are possible.